1. Field of the Invention
The present invention relates to a system and method for supervising a buffer memory hierarchy provided in a computer system comprised of a plurality of central processing units (each of which has a respective buffer memory therein), a plurality of channel processors, a main memory, an intermediate buffer memory commonly occupied by the buffer memories, channel processors and main memory.
A computer system which is comprised of a plurality of central processing units is usually called a multiprocessor system. In a multiprocessor system, it is important that a data block stored at an address in buffer memory in one processor always coincides with a data block to be stored at a corresponding address in buffer memory in the other processor. The latter condition is known as buffer memory coincidence.
In the prior art, there are two methods for achieving the above-mentioned buffer memory coincidence. A first method for achieving buffer memory coincidence is by the application of a buffer invalidation address simultaneously to all of the processors except for one processor when a data block stored at an address in buffer memory in the processor is changed. The above application of the buffer invalidation address to the buffer memories of all the processors except for one processor is performed regardless of whether the corresponding address of the buffer memory in each of the former processors is or is not found therein. This corresponding address is the same as the buffer invalidation address.
A second method for achieving the above-mentioned buffer memory coincidence is to provide, in each processor, a tag II as opposed to a conventional tag I. In this second method, the buffer invalidation address mentioned in the first method is applied only to the buffer memories which include corresponding addresses, in respective processors, by means of the tag II.
In the above-described conventional multiprocessor system, a memory system is comprised of a main memory and buffer memories contained in respective central processing units. In recent years, however, a new memory system for the conventional multiprocessor system has been proposed. In such a new memory system, as proposed in, for example, "Determining Hit Ratios for Multilevel Hierarchies", by J. Gesei, I.B.M. J. Res. Develop., July, 1974, or "On Memory System Design", by Robert M. Meade, FJCC, 1970, pages 33 through 34, an intermediate buffer memory is further inserted between the main memory and the buffer memories. When each central processing unit of the multiprocessor system becomes large in scale and high in operation speed, it is relatively easy to produce high speed operating buffer memories. However, with regard to the main memory, it is very difficult to produce a main memory which is large in scale and which, at the same time, has a high operating speed. Therefore, when each central processing unit of the multiprocessor system becomes large in size and high in operating speed, it is impossible to directly connect the main memory to the buffer memories without introducing an intermediate means therebetween. Thus, the above-mentioned intermediate buffer memory is employed as this intermediate means. The memory capacity of the intermediate buffer memory is larger than that of each buffer memory but smaller than that of the main memory. Also, the access time of the intermediate buffer memory is longer than that of each buffer memory but shorter than that of the main memory.
Thus, a better method and system for achieving buffer memory coincidence should be proposed. Such proposed method should be suitable for a memory system which includes the intermediate buffer memory. One method for achieving buffer memory coincidence is already known. In the multiprocessor system to which the known method is applied, there are a plurality of central processing units, a plurality of channel processors, an intermediate buffer memory, a main memory and a plurality of buffer memories contained in the respective central processing units. When the intermediate buffer memory receives, from one of the central processing units, a request for access of a data block of the buffer memory, the intermediate buffer memory starts detecting whether or not a corresponding data block is stored therein by means of a tag contained therein. If the corresponding data block is not stored therein, the intermediate buffer memory will determine which data block is to be replaced, and then the corresponding data block is moved into the address of this memory from the main memory, which address is the position where the replaced data block was stored in the intermediate buffer memory. The tag of the intermediate buffer memory is provided with a plurality of supervising information memory areas and data block memory areas. Each supervising information memory area contains both an address information of the data block stored in the corresponding data block memory area and copy flags for indicating which one of the buffer memories has a copy of the corresponding data block. When the intermediate buffer memory determines which of the above-mentioned data blocks is to be replaced, then the intermediate buffer memory checks the copy flags. As a result, the intermediate buffer memory sends the buffer invalidation address information only to buffer memories which store copies of the replaced data block. The buffer invalidation address is the same as the address of each of the buffer memories which has a copy of the replaced data block stored therein.
Contrary to the above, if the corresponding data block is stored in the intermediate buffer memory, when the intermediate buffer memory receives a request from one of the central processing units for access of the corresponding data block, and, further, when the request is a request for writing a data block, an address of this data block to be written is sent as the buffer invalidation address information only to every buffer memory containing a corresponding address from the intermediate buffer memory in accordance with the status of the copy flags. Alternatively, when such request is not a request for writing a data block but a request for reading a data block, it is not necessary to send the buffer invalidation address information from the intermediate buffer memory to the buffer memories.
An undesirable problem, as described hereinafter, exists in any multiprocessor system to which the above-mentioned known method is applied. When one central processing unit sends a request to the intermediate buffer memory for writing or reading a data block, and the corresponding data block is, however, not stored therein, the intermediate buffer memory then must determine which data block is to be replaced therefrom in order to move the corresponding data block from the main memory to the intermediate buffer memory. In this case, the address of the replaced data block is sent as buffer invalidation address information to each buffer memory containing a copy of the replaced data block in accordance with the status of the copy flags. Thereafter, copies of the replaced data block are erased from the respective buffer memories. However, if a particular central processing unit uses a copy of the replaced data block contained in the buffer memory of this central processing unit very frequently, it is not preferable for this central processing unit to erase the copy of the replaced data block from the buffer memory. Nevertheless, according to the known method, such copy is unfortunately erased therefrom and the above-mentioned undesirable problem therefore occurs because the intermediate buffer memory and the buffer memories are supervised in accordance with the method whereby the data blocks stored in at least one of the buffer memories must also be stored in the intermediate buffer memory.